In pipelined processors, a data hazard occurs when: MCQ with Answer and Explanation

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In pipelined processors, a data hazard occurs when:

A. Branches are predicted wrong

B. Clock speed is too high

C. An instruction depends on the result of a previous instruction still in pipeline

D. Cache miss happens

Answer: Option C

Solution (By JKExamLibrary)

Forwarding or stalls are used to resolve them.

This question belongs to: Computer CPU (Central Processing Unit)

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Practice More CPU (Central Processing Unit) Questions

Question #1 Report Error

CISC stands for:

A. Complex Instruction Set Computer

B. Central Integrated System Computer

C. Cache Instruction Set Computer

D. Control Instruction Set Computer

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Correct Answer: Option A

Explanation:
CISC uses complex multi-step instructions.

This question belongs to: Computer CPU (Central Processing Unit)

Question #2 Report Error

The loop stream detector:

A. Handles branches

B. Manages power

C. Detects cache misses

D. Recognizes and optimizes small loops

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Correct Answer: Option D

Explanation:
Reduces front-end power.

This question belongs to: Computer CPU (Central Processing Unit)

Question #3 Report Error

Which feature allows dynamic core frequency adjustment?

A. SpeedStep or Cool'n'Quiet

B. Static voltage

C. Fixed frequency

D. No adjustment

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Correct Answer: Option A

Explanation:
Intel and AMD power management.

This question belongs to: Computer CPU (Central Processing Unit)

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