Instruction level parallelism (ILP) is exploited by: MCQ with Answer and Explanation

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Instruction level parallelism (ILP) is exploited by:

A. Pipelining and superscalar designs

B. Software only

C. Memory

D. Single core only

Answer: Option A

Solution (By JKExamLibrary)

Hardware techniques maximize parallel instruction execution.

This question belongs to: Computer CPU (Central Processing Unit)

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Practice More CPU (Central Processing Unit) Questions

Question #1 Report Error

Integrated memory controller (IMC) reduces:

A. Power efficiency

B. Memory access latency

C. Core speed

D. Cache performance

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Correct Answer: Option B

Explanation:
On-die controller.

This question belongs to: Computer CPU (Central Processing Unit)

Question #2 Report Error

Which component is responsible for instruction sequencing?

A. Cache

B. Program Counter in CU

C. ALU

D. I/O ports

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Correct Answer: Option B

Explanation:
Program Counter manages the sequence of instruction fetch.

This question belongs to: Computer CPU (Central Processing Unit)

Question #3 Report Error

Prefetching in CPU aims to:

A. Limit registers

B. Reduce cache misses by loading data early

C. Increase power usage

D. Slow down execution

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Correct Answer: Option B

Explanation:
Hardware or software prefetchers anticipate needs.

This question belongs to: Computer CPU (Central Processing Unit)

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