The fetch width in superscalar CPUs refers to: MCQ with Answer and Explanation

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The fetch width in superscalar CPUs refers to:

A. Cache line

B. Register size

C. Number of instructions fetched per cycle

D. Data bus width

Answer: Option C

Solution (By JKExamLibrary)

Affects instruction throughput.

This question belongs to: Computer CPU (Central Processing Unit)

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Practice More CPU (Central Processing Unit) Questions

Question #1 Report Error

Secure Boot is supported by CPU through:

A. Software only

B. Cache encryption

C. Hardware root of trust

D. ALU modifications

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Correct Answer: Option C

Explanation:
Like TPM integration.

This question belongs to: Computer CPU (Central Processing Unit)

Question #2 Report Error

Multi-socket systems use:

A. UMA only

B. No interconnect

C. Single memory pool

D. NUMA architecture

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Correct Answer: Option D

Explanation:
Non-Uniform Memory Access.

This question belongs to: Computer CPU (Central Processing Unit)

Question #3 Report Error

RISC-V is an example of:

A. Proprietary CISC design

B. Open-source Instruction Set Architecture

C. Graphics processor

D. Memory controller

View Answer & Solution Discuss

Correct Answer: Option B

Explanation:
It is a royalty-free RISC ISA.

This question belongs to: Computer CPU (Central Processing Unit)

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