CPU (Central Processing Unit) MCQs

Practice CPU MCQs with answers and explanations covering ALU, CU, registers, processors and central processing unit concepts frequently asked in competitive exams.

327 Total
Question #161 Report Error
The dispatch buffer holds:
A. Instructions ready for execution
B. Committed results
C. Addresses only
D. Fetched but not decoded

Correct Answer: Option A


Explanation:
In out-of-order processors.

This question belongs to: Computer CPU (Central Processing Unit)
Question #162 Report Error
Heterogeneous System Architecture (HSA) promotes:
A. Seamless CPU-GPU integration
B. Separation of units
C. Software incompatibility
D. No sharing

Correct Answer: Option A


Explanation:
Unified memory and programming.

This question belongs to: Computer CPU (Central Processing Unit)
Question #163 Report Error
A high core count CPU is best for:
A. Basic office work exclusively
B. Single threaded games only
C. No applications
D. Highly parallel workloads like rendering

Correct Answer: Option D


Explanation:
Scales with thread-heavy tasks.

This question belongs to: Computer CPU (Central Processing Unit)
Question #164 Report Error
The predictor in branch prediction can be:
A. Only hardware
B. Software irrelevant
C. Static or dynamic
D. No predictor

Correct Answer: Option C


Explanation:
Dynamic uses history for accuracy.

This question belongs to: Computer CPU (Central Processing Unit)
Question #165 Report Error
Which company leads in discrete GPU but also makes CPUs?
A. NVIDIA has CPUs too but AMD/Intel primary
B. Focus on one
C. None
D. All do equally

Correct Answer: Option A


Explanation:
AMD integrates well with Radeon.

This question belongs to: Computer CPU (Central Processing Unit)
Question #166 Report Error
The store queue handles:
A. ALU results
B. Fetches
C. Pending memory writes
D. Decodes

Correct Answer: Option C


Explanation:
For memory ordering.

This question belongs to: Computer CPU (Central Processing Unit)
Question #167 Report Error
Advanced topics in 2026 CPU include more emphasis on:
A. Analog signals
B. Sustainability, AI, and security
C. Basic functions only
D. Ignoring heat

Correct Answer: Option B


Explanation:
Modern design priorities.

This question belongs to: Computer CPU (Central Processing Unit)
Question #168 Report Error
The front-end of CPU pipeline includes:
A. Memory access
B. Fetch and decode
C. Execute only
D. Writeback

Correct Answer: Option B


Explanation:
Prepares instructions for execution.

This question belongs to: Computer CPU (Central Processing Unit)
Question #169 Report Error
Back-end focuses on:
A. Addressing
B. Fetching
C. Decoding
D. Execution and retirement

Correct Answer: Option D


Explanation:
Carrying out and completing instructions.

This question belongs to: Computer CPU (Central Processing Unit)
Question #170 Report Error
Which is critical for cloud computing CPUs?
A. Consumer features
B. Gaming graphics
C. High density, security, and virtualization support
D. Low core count

Correct Answer: Option C


Explanation:
Optimized for multi-tenant environments.

This question belongs to: Computer CPU (Central Processing Unit)
Question #171 Report Error
The load queue manages:
A. ALU
B. Writes only
C. Pending memory reads
D. Control

Correct Answer: Option C


Explanation:
For memory operations in pipeline.

This question belongs to: Computer CPU (Central Processing Unit)
Question #172 Report Error
Monolithic die vs chiplet trade-off is in:
A. Only size
B. Performance, cost, and yield
C. Power irrelevant
D. No difference

Correct Answer: Option B


Explanation:
Chiplets offer scalability.

This question belongs to: Computer CPU (Central Processing Unit)
Question #173 Report Error
Which feature helps in side-channel attack mitigation?
A. Higher clock
B. Larger cache
C. More registers
D. Hardware security enhancements

Correct Answer: Option D


Explanation:
Constant time operations and isolation.

This question belongs to: Computer CPU (Central Processing Unit)
Question #174 Report Error
The retirement rate depends on:
A. Pipeline width and dependencies
B. Input devices
C. External bus
D. Memory size

Correct Answer: Option A


Explanation:
How quickly instructions complete.

This question belongs to: Computer CPU (Central Processing Unit)
Question #175 Report Error
Upcoming CPUs focus on:
A. Slower speeds
B. Ignoring AI
C. Energy efficiency and specialized accelerators
D. Basic design

Correct Answer: Option C


Explanation:
To meet demands of modern computing.

This question belongs to: Computer CPU (Central Processing Unit)
Question #176 Report Error
The shadow registers or checkpointing is for:
A. Normal operations
B. Speculative execution recovery
C. Display
D. Storage

Correct Answer: Option B


Explanation:
To rollback on mis-speculation.

This question belongs to: Computer CPU (Central Processing Unit)
Question #177 Report Error
Which is a key metric for laptop CPUs?
A. Core count irrelevant
B. Maximum TDP only
C. Size of packaging
D. Performance per watt and thermal envelope

Correct Answer: Option D


Explanation:
Balances performance and battery life.

This question belongs to: Computer CPU (Central Processing Unit)
Question #178 Report Error
The von Neumann bottleneck primarily refers to:
A. Limited memory bandwidth between CPU and memory
B. Register access time
C. ALU processing speed
D. Control unit delays

Correct Answer: Option A


Explanation:
The shared bus for data and instructions limits throughput in von Neumann architecture.

This question belongs to: Computer CPU (Central Processing Unit)
Question #179 Report Error
In CPU design, 'IPC' stands for:
A. Integrated Power Control
B. Instructions Per Cycle
C. Interrupt Priority Controller
D. Internal Processing Cache

Correct Answer: Option B


Explanation:
IPC measures how many instructions a CPU executes per clock cycle.

This question belongs to: Computer CPU (Central Processing Unit)
Question #180 Report Error
Which register is used to store the return address during subroutine calls?
A. Link Register
B. Flag Register
C. Program Counter
D. Accumulator

Correct Answer: Option A


Explanation:
Link Register (in many architectures) holds the return address.

This question belongs to: Computer CPU (Central Processing Unit)