CPU (Central Processing Unit) MCQs

Practice CPU MCQs with answers and explanations covering ALU, CU, registers, processors and central processing unit concepts frequently asked in competitive exams.

327 Total

Question #181 Report Error

The Harvard architecture differs from von Neumann by having:

A. No registers

B. Slower processing

C. Shared memory only

D. Separate buses and memory for instructions and data

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Correct Answer: Option D

Explanation:
This allows simultaneous instruction fetch and data access.

This question belongs to: Computer CPU (Central Processing Unit)

Question #182 Report Error

What does the acronym FPU stand for in CPU context?

A. Flag Processing Unit

B. Fast Processing Unit

C. Fetch Pipeline Unit

D. Floating Point Unit

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Correct Answer: Option D

Explanation:
FPU handles floating-point arithmetic operations.

This question belongs to: Computer CPU (Central Processing Unit)

Question #183 Report Error

Branch misprediction leads to:

A. Pipeline flush and performance loss

B. Reduced power consumption

C. Increased clock speed

D. Better cache hit rate

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Correct Answer: Option A

Explanation:
Wrong prediction requires discarding speculative work.

This question belongs to: Computer CPU (Central Processing Unit)

Question #184 Report Error

L3 cache is typically:

A. Slower than registers but faster than RAM

B. Private to each core

C. Shared among all CPU cores

D. Used only for instructions

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Correct Answer: Option C

Explanation:
It acts as a larger shared cache layer.

This question belongs to: Computer CPU (Central Processing Unit)

Question #185 Report Error

The Memory Management Unit (MMU) is responsible for:

A. Power management

B. Instruction decoding

C. Virtual to physical address translation

D. Arithmetic calculations

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Correct Answer: Option C

Explanation:
MMU handles memory protection and address mapping.

This question belongs to: Computer CPU (Central Processing Unit)

Question #186 Report Error

Which of the following is a CISC characteristic?

A. Fixed length instructions

B. Complex multi-cycle instructions

C. Simple pipeline

D. Large number of registers

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Correct Answer: Option B

Explanation:
CISC instructions can perform multiple low-level operations.

This question belongs to: Computer CPU (Central Processing Unit)

Question #187 Report Error

SIMD stands for:

A. Sequential Instruction Multiple Decode

B. Shared Instruction Memory Data

C. Single Instruction Multiple Data

D. System Integrated Memory Device

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Correct Answer: Option C

Explanation:
SIMD allows one instruction to process multiple data elements.

This question belongs to: Computer CPU (Central Processing Unit)

Question #188 Report Error

The purpose of a TLB is to:

A. Store temporary data

B. Cache recent virtual-to-physical address mappings

C. Manage interrupts

D. Control ALU operations

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Correct Answer: Option B

Explanation:
TLB speeds up address translation.

This question belongs to: Computer CPU (Central Processing Unit)

Question #189 Report Error

In pipelined processors, a data hazard occurs when:

A. Clock speed is too high

B. Cache miss happens

C. An instruction depends on the result of a previous instruction still in pipeline

D. Branches are predicted wrong

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Correct Answer: Option C

Explanation:
Forwarding or stalls are used to resolve them.

This question belongs to: Computer CPU (Central Processing Unit)

Question #190 Report Error

Which technology allows a single physical core to execute two threads?

A. Multi-core processing

B. Cache coherence

C. Simultaneous Multithreading (SMT)

D. Overclocking

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Correct Answer: Option C

Explanation:
SMT improves resource utilization.

This question belongs to: Computer CPU (Central Processing Unit)

Question #191 Report Error

The term 'process node' like 5nm refers to:

A. Clock frequency

B. Cache size

C. Semiconductor manufacturing technology

D. Number of CPU cores

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Correct Answer: Option C

Explanation:
Smaller nodes improve density and efficiency.

This question belongs to: Computer CPU (Central Processing Unit)

Question #192 Report Error

Which bus carries memory addresses from CPU?

A. Address Bus

B. System Bus

C. Control Bus

D. Data Bus

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Correct Answer: Option A

Explanation:
Address bus specifies memory locations.

This question belongs to: Computer CPU (Central Processing Unit)

Question #193 Report Error

Out-of-order execution primarily helps overcome:

A. Control flow changes

B. Memory capacity limits

C. Data dependencies and stalls

D. Power constraints

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Correct Answer: Option C

Explanation:
It reorders instructions for better throughput.

This question belongs to: Computer CPU (Central Processing Unit)

Question #194 Report Error

The accumulator register is most commonly associated with:

A. Storing status flags

B. Holding instruction addresses

C. Storing ALU operation results

D. Managing stack operations

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Correct Answer: Option C

Explanation:
It serves as a default destination for results.

This question belongs to: Computer CPU (Central Processing Unit)

Question #195 Report Error

Chiplet-based CPU design offers advantages in:

A. Simpler manufacturing

B. Lower power always

C. Single die performance only

D. Cost, yield, and scalability

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Correct Answer: Option D

Explanation:
Multiple smaller dies are connected.

This question belongs to: Computer CPU (Central Processing Unit)

Question #196 Report Error

Which flag indicates arithmetic overflow?

A. Overflow flag

B. Sign flag

C. Zero flag

D. Carry flag

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Correct Answer: Option A

Explanation:
It signals when a result exceeds representable range.

This question belongs to: Computer CPU (Central Processing Unit)

Question #197 Report Error

RISC-V is an example of:

A. Graphics processor

B. Proprietary CISC design

C. Open-source Instruction Set Architecture

D. Memory controller

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Correct Answer: Option C

Explanation:
It is a royalty-free RISC ISA.

This question belongs to: Computer CPU (Central Processing Unit)

Question #198 Report Error

The write-back cache policy updates main memory:

A. Immediately on every write

B. Only on read

C. When the cache line is evicted

D. Never

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Correct Answer: Option C

Explanation:
It minimizes memory traffic.

This question belongs to: Computer CPU (Central Processing Unit)

Question #199 Report Error

Superscalar processors can issue:

A. Instructions out of order only

B. One instruction only

C. No instructions

D. Multiple instructions per clock cycle

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Correct Answer: Option D

Explanation:
They have multiple execution units.

This question belongs to: Computer CPU (Central Processing Unit)

Question #200 Report Error

Which component manages interrupt requests in CPU?

A. Control Unit

B. Registers only

C. ALU

D. Cache controller

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Correct Answer: Option A

Explanation:
It saves context and transfers control to ISR.

This question belongs to: Computer CPU (Central Processing Unit)

CPU (Central Processing Unit) MCQs

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