CPU (Central Processing Unit) MCQs

Practice CPU MCQs with answers and explanations covering ALU, CU, registers, processors and central processing unit concepts frequently asked in competitive exams.

327 Total

Question #221 Report Error

The load/store architecture restricts memory access to:

A. Dedicated load and store instructions

B. Control unit

C. ALU only

D. All instructions

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Correct Answer: Option A

Explanation:
Typical in RISC designs.

This question belongs to: Computer CPU (Central Processing Unit)

Question #222 Report Error

Hyper-threading is Intel's implementation of:

A. Cache prefetch

B. Overclocking

C. Multi-core

D. Simultaneous Multithreading

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Correct Answer: Option D

Explanation:
It presents one core as multiple logical processors.

This question belongs to: Computer CPU (Central Processing Unit)

Question #223 Report Error

Which cache level is usually smallest and fastest?

A. L4 Cache

B. L3 Cache

C. L1 Cache

D. L2 Cache

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Correct Answer: Option C

Explanation:
Split into instruction and data caches per core.

This question belongs to: Computer CPU (Central Processing Unit)

Question #224 Report Error

The opcode fetch is part of:

A. Write-back stage

B. Memory stage

C. Instruction fetch stage

D. Execution stage

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Correct Answer: Option C

Explanation:
First step in processing an instruction.

This question belongs to: Computer CPU (Central Processing Unit)

Question #225 Report Error

EPIC architecture was used in:

A. Modern x86

B. Intel Itanium processors

C. ARM mobiles

D. Embedded controllers

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Correct Answer: Option B

Explanation:
Explicitly Parallel Instruction Computing.

This question belongs to: Computer CPU (Central Processing Unit)

Question #226 Report Error

A CPU's TDP rating indicates:

A. Thread Distribution Protocol

B. Transistor Density Parameter

C. Thermal Design Power

D. Total Data Processed

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Correct Answer: Option C

Explanation:
Maximum heat output under sustained load.

This question belongs to: Computer CPU (Central Processing Unit)

Question #227 Report Error

A. Control hazards

B. Write-after-read and write-after-write hazards

C. Interrupt handling

D. Cache misses

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Correct Answer: Option B

Explanation:
It eliminates false dependencies.

This question belongs to: Computer CPU (Central Processing Unit)

Question #228 Report Error

The base clock (BCLK) in Intel systems affects:

A. Network interface

B. Only GPU

C. CPU, memory, and bus frequencies

D. Storage speed

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Correct Answer: Option C

Explanation:
It is the reference frequency.

This question belongs to: Computer CPU (Central Processing Unit)

Question #229 Report Error

Which is a benefit of multi-chip module (MCM) design?

A. Better binning and cost efficiency

B. Simpler cooling

C. Higher single-thread latency

D. Reduced core communication

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Correct Answer: Option A

Explanation:
Used in many modern high-core CPUs.

This question belongs to: Computer CPU (Central Processing Unit)

Question #230 Report Error

The zero flag is set when:

A. Negative result

B. Overflow happens

C. Carry occurs

D. Result of operation is zero

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Correct Answer: Option D

Explanation:
Useful for conditional branching.

This question belongs to: Computer CPU (Central Processing Unit)

Question #231 Report Error

NPU in modern processors accelerates:

A. Graphics rendering

B. Neural network and AI computations

C. Basic integer math

D. Storage access

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Correct Answer: Option B

Explanation:
Dedicated for machine learning tasks.

This question belongs to: Computer CPU (Central Processing Unit)

Question #232 Report Error

Instruction fusion combines:

A. Cores

B. Buses

C. Caches

D. Multiple instructions into one micro-op

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Correct Answer: Option D

Explanation:
Improves decode and execution efficiency.

This question belongs to: Computer CPU (Central Processing Unit)

Question #233 Report Error

Which architecture uses condition codes extensively?

A. Quantum processors

B. No modern CPU

C. Many RISC designs

D. Only CISC

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Correct Answer: Option C

Explanation:
Flags guide conditional execution.

This question belongs to: Computer CPU (Central Processing Unit)

Question #234 Report Error

The ring interconnect is used in:

A. External I/O

B. Power delivery

C. Memory access only

D. Intel CPUs for core communication

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Correct Answer: Option D

Explanation:
Provides high bandwidth between cores.

This question belongs to: Computer CPU (Central Processing Unit)

Question #235 Report Error

Overclocking primarily increases:

A. Cache size

B. Number of cores

C. Memory capacity

D. Clock frequency beyond stock

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Correct Answer: Option D

Explanation:
Requires better cooling and stability testing.

This question belongs to: Computer CPU (Central Processing Unit)

Question #236 Report Error

The microcode ROM is part of:

A. Registers

B. ALU

C. Cache

D. Control Unit in CISC processors

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Correct Answer: Option D

Explanation:
It translates complex instructions.

This question belongs to: Computer CPU (Central Processing Unit)

Question #237 Report Error

Which feature is important for server CPUs?

A. Gaming optimizations only

B. Low power mobile focus

C. Integrated graphics priority

D. High core count and ECC memory support

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Correct Answer: Option D

Explanation:
Reliability and scalability.

This question belongs to: Computer CPU (Central Processing Unit)

Question #238 Report Error

The store buffer holds:

A. Data waiting to be written to memory

B. Branch targets

C. Fetched instructions

D. Decoded uops

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Correct Answer: Option A

Explanation:
It allows execution to continue.

This question belongs to: Computer CPU (Central Processing Unit)

Question #239 Report Error

Big.LITTLE processing is a form of:

A. Asymmetric multi-processing

B. No power management

C. Single core

D. Symmetric only

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Correct Answer: Option A

Explanation:
Mix of high-performance and efficient cores.

This question belongs to: Computer CPU (Central Processing Unit)

Question #240 Report Error

Which instruction set supports 256-bit vectors?

A. MMX

B. AVX2

C. SSE only

D. x87

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Correct Answer: Option B

Explanation:
Advanced Vector Extensions 2.

This question belongs to: Computer CPU (Central Processing Unit)

CPU (Central Processing Unit) MCQs

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