CPU (Central Processing Unit) MCQs

Practice CPU MCQs with answers and explanations covering ALU, CU, registers, processors and central processing unit concepts frequently asked in competitive exams.

327 Total

Question #261 Report Error

Flag register is also called:

A. Stack Pointer

B. Status Register or EFLAGS

C. Accumulator

D. Program Counter

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Correct Answer: Option B

Explanation:
Contains condition codes.

This question belongs to: Computer CPU (Central Processing Unit)

Question #262 Report Error

Turbo Boost in Intel CPUs allows:

A. Core disabling

B. Frequency decrease

C. Cache reduction

D. Automatic frequency increase under load

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Correct Answer: Option D

Explanation:
Within power and thermal limits.

This question belongs to: Computer CPU (Central Processing Unit)

Question #263 Report Error

The decode unit converts:

A. Results to output

B. High-level code

C. Machine code to internal micro-ops

D. Addresses to data

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Correct Answer: Option C

Explanation:
Prepares for execution.

This question belongs to: Computer CPU (Central Processing Unit)

Question #264 Report Error

Which is a disadvantage of very deep pipelines?

A. Higher branch misprediction penalty

B. Lower clock speeds

C. Simpler hazard detection

D. Reduced power

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Correct Answer: Option A

Explanation:
More stages to flush.

This question belongs to: Computer CPU (Central Processing Unit)

Question #265 Report Error

The memory ordering model in x86 is:

A. Strongly ordered with some relaxations

B. Weakly ordered always

C. No ordering

D. ARM style

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Correct Answer: Option A

Explanation:
Ensures consistency.

This question belongs to: Computer CPU (Central Processing Unit)

Question #266 Report Error

Precision Boost Overdrive (PBO) is an AMD feature for:

A. Power saving

B. Aggressive automatic overclocking

C. Core parking

D. Cache clearing

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Correct Answer: Option B

Explanation:
Uses extra power headroom.

This question belongs to: Computer CPU (Central Processing Unit)

Question #267 Report Error

The branch target buffer (BTB) stores:

A. Status flags

B. Addresses of taken branches

C. Instruction opcodes

D. Data values

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Correct Answer: Option B

Explanation:
For faster branch prediction.

This question belongs to: Computer CPU (Central Processing Unit)

Question #268 Report Error

Which unit performs logical operations like AND, OR?

A. ALU

B. Register file

C. CU only

D. Cache controller

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Correct Answer: Option A

Explanation:
Part of arithmetic logic capabilities.

This question belongs to: Computer CPU (Central Processing Unit)

Question #269 Report Error

SoC stands for:

A. Single Operation Core

B. System on Chip

C. Secure Operation Channel

D. System on Cache

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Correct Answer: Option B

Explanation:
Integrates CPU, GPU, etc.

This question belongs to: Computer CPU (Central Processing Unit)

Question #270 Report Error

The issue width determines:

A. How many instructions can be issued per cycle

B. TDP rating

C. Memory size

D. Cache associativity

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Correct Answer: Option A

Explanation:
Key superscalar parameter.

This question belongs to: Computer CPU (Central Processing Unit)

Question #271 Report Error

Guard pages and stack canaries are:

A. Unrelated to CPU

B. Software security features supported by CPU

C. Power features

D. Hardware only

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Correct Answer: Option B

Explanation:
Prevent exploits.

This question belongs to: Computer CPU (Central Processing Unit)

Question #272 Report Error

The L2 cache is typically:

A. Slower than L1

B. Per-core private cache

C. Fully shared

D. Instruction only

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Correct Answer: Option B

Explanation:
Balances speed and size.

This question belongs to: Computer CPU (Central Processing Unit)

Question #273 Report Error

Which company uses 'Golden Cove' architecture?

A. AMD

B. Apple

C. Intel

D. ARM

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Correct Answer: Option C

Explanation:
Part of recent Intel cores.

This question belongs to: Computer CPU (Central Processing Unit)

Question #274 Report Error

Return stack buffer helps predict:

A. Cache hits

B. Function returns accurately

C. ALU results

D. Data loads

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Correct Answer: Option B

Explanation:
For CALL/RET pairs.

This question belongs to: Computer CPU (Central Processing Unit)

Question #275 Report Error

The von Neumann model uses:

A. Separate data buses only

B. No memory

C. Stored program concept

D. Quantum bits

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Correct Answer: Option C

Explanation:
Instructions and data in same memory.

This question belongs to: Computer CPU (Central Processing Unit)

Question #276 Report Error

FMA instruction stands for:

A. Fetch Memory Address

B. Flag Management Algorithm

C. Fused Multiply-Add

D. Fast Memory Access

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Correct Answer: Option C

Explanation:
Performs multiplication and addition in one step.

This question belongs to: Computer CPU (Central Processing Unit)

Question #277 Report Error

Which is essential for virtualization?

A. Basic ALU

B. Hardware-assisted virtualization extensions

C. Low core count

D. Small cache

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Correct Answer: Option B

Explanation:
Like VT-x or AMD-V.

This question belongs to: Computer CPU (Central Processing Unit)

Question #278 Report Error

The pipeline stall due to structural hazard happens when:

A. Cache miss

B. Two instructions need the same hardware resource

C. Branch taken

D. Data dependency

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Correct Answer: Option B

Explanation:
Resource conflict.

This question belongs to: Computer CPU (Central Processing Unit)

Question #279 Report Error

Apple's Firestorm cores are part of:

A. GPU only

B. M-series ARM-based CPUs

C. Server chips

D. x86 processors

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Correct Answer: Option B

Explanation:
High performance mobile/desktop SoCs.

This question belongs to: Computer CPU (Central Processing Unit)

Question #280 Report Error

The data cache (D-cache) handles:

A. Control signals

B. Instruction fetch

C. ALU internal

D. Load and store operations

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Correct Answer: Option D

Explanation:
Separate from I-cache.

This question belongs to: Computer CPU (Central Processing Unit)

CPU (Central Processing Unit) MCQs

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