CPU (Central Processing Unit) MCQs

Practice CPU MCQs with answers and explanations covering ALU, CU, registers, processors and central processing unit concepts frequently asked in competitive exams.

327 Total

Question #301 Report Error

The instruction cache primarily stores:

A. Data operands

B. Frequently used instructions

C. Addresses

D. Results

View Answer & Solution Discuss

Correct Answer: Option B

Explanation:
To speed up fetch stage.

This question belongs to: Computer CPU (Central Processing Unit)

Question #302 Report Error

Multi-socket systems use:

A. No interconnect

B. UMA only

C. NUMA architecture

D. Single memory pool

View Answer & Solution Discuss

Correct Answer: Option C

Explanation:
Non-Uniform Memory Access.

This question belongs to: Computer CPU (Central Processing Unit)

Question #303 Report Error

The retirement queue tracks:

A. Instructions in flight for in-order commit

B. Memory requests

C. Fetched only

D. Decoded uops

View Answer & Solution Discuss

Correct Answer: Option A

Explanation:
Maintains correctness.

This question belongs to: Computer CPU (Central Processing Unit)

Question #304 Report Error

Which is a key design goal for laptop CPUs?

A. Unlimited power

B. Maximum TDP

C. Desktop level heat

D. High performance within thermal and power limits

View Answer & Solution Discuss

Correct Answer: Option D

Explanation:
Balances battery and performance.

This question belongs to: Computer CPU (Central Processing Unit)

Question #305 Report Error

The fused multiply-add improves:

A. Integer ops only

B. Accuracy and performance in floating point

C. Branch prediction

D. Memory bandwidth

View Answer & Solution Discuss

Correct Answer: Option B

Explanation:
Single rounding error.

This question belongs to: Computer CPU (Central Processing Unit)

Question #306 Report Error

Cache line size is typically:

A. 1024 bytes

B. 64 bytes

C. 1 byte

D. 8 bytes

View Answer & Solution Discuss

Correct Answer: Option B

Explanation:
Unit of transfer between cache levels.

This question belongs to: Computer CPU (Central Processing Unit)

Question #307 Report Error

Hardware transactional memory (HTM) allows:

A. Software locks

B. No concurrency

C. Speculative concurrent transactions

D. Sequential execution only

View Answer & Solution Discuss

Correct Answer: Option C

Explanation:
Like Intel TSX.

This question belongs to: Computer CPU (Central Processing Unit)

Question #308 Report Error

The decode stage may involve:

A. No decoding

B. Complex decoding for variable length instructions

C. Simple fixed length only

D. ALU computation

View Answer & Solution Discuss

Correct Answer: Option B

Explanation:
In x86 especially.

This question belongs to: Computer CPU (Central Processing Unit)

Question #309 Report Error

Which supports better multi-thread scaling?

A. Fewer cores

B. Low frequency

C. Small cache

D. Larger last level cache and interconnect

View Answer & Solution Discuss

Correct Answer: Option D

Explanation:
Reduces contention.

This question belongs to: Computer CPU (Central Processing Unit)

Question #310 Report Error

The status of 'dirty' bit in cache indicates:

A. Invalid entry

B. Clean data

C. Shared data

D. Modified data needing write-back

View Answer & Solution Discuss

Correct Answer: Option D

Explanation:
For write-back policy.

This question belongs to: Computer CPU (Central Processing Unit)

Question #311 Report Error

Future CPU trends include more:

A. General purpose only

B. Domain specific accelerators

C. Analog computing

D. Reduced specialization

View Answer & Solution Discuss

Correct Answer: Option B

Explanation:
For AI, graphics, etc.

This question belongs to: Computer CPU (Central Processing Unit)

Question #312 Report Error

The jump register instruction uses:

A. Stack top

B. Memory indirect

C. Immediate only

D. Register value as target address

View Answer & Solution Discuss

Correct Answer: Option D

Explanation:
For indirect jumps.

This question belongs to: Computer CPU (Central Processing Unit)

Question #313 Report Error

Which mitigates Meltdown vulnerability?

A. Cache increase

B. More ALUs

C. Higher clock

D. Kernel page table isolation and hardware fixes

View Answer & Solution Discuss

Correct Answer: Option D

Explanation:
Separation of user and kernel memory.

This question belongs to: Computer CPU (Central Processing Unit)

Question #314 Report Error

The execution cluster in CPU may contain:

A. Control logic

B. Single unit

C. Cache only

D. Multiple ALUs, FPUs, load/store units

View Answer & Solution Discuss

Correct Answer: Option D

Explanation:
For parallel execution.

This question belongs to: Computer CPU (Central Processing Unit)

Question #315 Report Error

A stride prefetcher predicts:

A. Power states

B. Access patterns with regular intervals

C. Random access

D. Branch targets

View Answer & Solution Discuss

Correct Answer: Option B

Explanation:
Common in array accesses.

This question belongs to: Computer CPU (Central Processing Unit)

Question #316 Report Error

The x86 ISA is:

A. Backward compatible across generations

B. RISC based

C. Fixed 32-bit

D. Completely new each time

View Answer & Solution Discuss

Correct Answer: Option A

Explanation:
Maintains compatibility.

This question belongs to: Computer CPU (Central Processing Unit)

Question #317 Report Error

Integrated memory controller (IMC) reduces:

A. Power efficiency

B. Cache performance

C. Core speed

D. Memory access latency

View Answer & Solution Discuss

Correct Answer: Option D

Explanation:
On-die controller.

This question belongs to: Computer CPU (Central Processing Unit)

Question #318 Report Error

Which is used for high performance computing?

A. Single core low power

B. Basic embedded

C. Many core CPUs with high bandwidth memory

D. Mobile SoCs

View Answer & Solution Discuss

Correct Answer: Option C

Explanation:
Like in supercomputers.

This question belongs to: Computer CPU (Central Processing Unit)

Question #319 Report Error

The predicate register in some ISAs enables:

A. ALU bypass

B. Memory only

C. Guarded execution

D. No conditional

View Answer & Solution Discuss

Correct Answer: Option C

Explanation:
Avoids branches.

This question belongs to: Computer CPU (Central Processing Unit)

Question #320 Report Error

CPU security features like CET protect against:

A. Data leaks only

B. Thermal issues

C. Control flow attacks

D. Power attacks

View Answer & Solution Discuss

Correct Answer: Option C

Explanation:
Intel Control-flow Enforcement Technology.

This question belongs to: Computer CPU (Central Processing Unit)

CPU (Central Processing Unit) MCQs

More Computer Topics