CPU (Central Processing Unit) MCQs

Practice CPU MCQs with answers and explanations covering ALU, CU, registers, processors and central processing unit concepts frequently asked in competitive exams.

327 Total

Question #281 Report Error

Which metric combines clock speed and IPC?

A. Cache hit rate

B. Overall performance in benchmarks

C. Core temperature

D. TDP only

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Correct Answer: Option B

Explanation:
Determines effective speed.

This question belongs to: Computer CPU (Central Processing Unit)

Question #282 Report Error

The shadow stack is a security feature for:

A. Protecting return addresses

B. Data encryption

C. Cache protection

D. Power management

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Correct Answer: Option A

Explanation:
Against ROP attacks.

This question belongs to: Computer CPU (Central Processing Unit)

Question #283 Report Error

Multi-level cache hierarchy reduces:

A. Average memory access time

B. Instruction set

C. Clock frequency

D. Core count

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Correct Answer: Option A

Explanation:
Exploits locality.

This question belongs to: Computer CPU (Central Processing Unit)

Question #284 Report Error

The control bus carries:

A. Signals like read/write, interrupt

B. Memory addresses

C. Data values

D. ALU operands

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Correct Answer: Option A

Explanation:
Commands and status.

This question belongs to: Computer CPU (Central Processing Unit)

Question #285 Report Error

Zen architecture introduced significant improvements in:

A. Single core legacy

B. Mobile power

C. Only clock speed

D. IPC and cache subsystem

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Correct Answer: Option D

Explanation:
AMD's modern core design.

This question belongs to: Computer CPU (Central Processing Unit)

Question #286 Report Error

The instruction window in out-of-order CPUs refers to:

A. Fetch buffer

B. Set of instructions being considered for execution

C. Cache lines

D. Retirement queue

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Correct Answer: Option B

Explanation:
For scheduling.

This question belongs to: Computer CPU (Central Processing Unit)

Question #287 Report Error

Which is a common mobile CPU series?

A. AMD Threadripper

B. Intel Core i9

C. Qualcomm Snapdragon

D. EPYC

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Correct Answer: Option C

Explanation:
ARM-based for smartphones.

This question belongs to: Computer CPU (Central Processing Unit)

Question #288 Report Error

The bypass network in pipeline is for:

A. Flushing

B. Stalling pipeline

C. Decoding

D. Forwarding results directly

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Correct Answer: Option D

Explanation:
Avoids data hazards.

This question belongs to: Computer CPU (Central Processing Unit)

Question #289 Report Error

Secure Boot is supported by CPU through:

A. Software only

B. Cache encryption

C. ALU modifications

D. Hardware root of trust

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Correct Answer: Option D

Explanation:
Like TPM integration.

This question belongs to: Computer CPU (Central Processing Unit)

Question #290 Report Error

The associativity in cache means:

A. Speed of access

B. Write policy

C. Number of places a block can go

D. Size of cache

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Correct Answer: Option C

Explanation:
Affects conflict misses.

This question belongs to: Computer CPU (Central Processing Unit)

Question #291 Report Error

Which generation of Ryzen uses chiplet design extensively?

A. Mobile only

B. Intel equivalent

C. First generation only

D. Ryzen 5000 and later

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Correct Answer: Option D

Explanation:
For scalability.

This question belongs to: Computer CPU (Central Processing Unit)

Question #292 Report Error

The exception handling in CPU involves:

A. Cache flush only

B. ALU reset

C. Precise interrupts and state saving

D. Ignoring errors

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Correct Answer: Option C

Explanation:
For errors and interrupts.

This question belongs to: Computer CPU (Central Processing Unit)

Question #293 Report Error

Graphene or future materials may impact:

A. Software

B. Cooling only

C. Transistor technology beyond silicon

D. Current designs

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Correct Answer: Option C

Explanation:
Potential for better performance.

This question belongs to: Computer CPU (Central Processing Unit)

Question #294 Report Error

The loop stream detector:

A. Recognizes and optimizes small loops

B. Detects cache misses

C. Handles branches

D. Manages power

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Correct Answer: Option A

Explanation:
Reduces front-end power.

This question belongs to: Computer CPU (Central Processing Unit)

Question #295 Report Error

Which is true about embedded CPUs?

A. Focus on real-time response and low power

B. Many threads

C. High performance gaming

D. Large cache priority

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Correct Answer: Option A

Explanation:
Used in IoT and appliances.

This question belongs to: Computer CPU (Central Processing Unit)

Question #296 Report Error

The architectural registers are:

A. Cache lines

B. Hidden physical only

C. Visible to software

D. Memory locations

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Correct Answer: Option C

Explanation:
Part of ISA.

This question belongs to: Computer CPU (Central Processing Unit)

Question #297 Report Error

Intel's EMIB technology is for:

A. Efficient chiplet packaging

B. Power delivery

C. Graphics only

D. Software emulation

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Correct Answer: Option A

Explanation:
Embedded Multi-Die Interconnect Bridge.

This question belongs to: Computer CPU (Central Processing Unit)

Question #298 Report Error

A higher clock speed with lower IPC may perform:

A. Worse always

B. Always better

C. Differently depending on workload

D. Same as low clock high IPC

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Correct Answer: Option C

Explanation:
Balance is key.

This question belongs to: Computer CPU (Central Processing Unit)

Question #299 Report Error

The vector mask in AVX allows:

A. Scalar only

B. Conditional execution in SIMD

C. No operations

D. Address masking

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Correct Answer: Option B

Explanation:
Efficient for predicated operations.

This question belongs to: Computer CPU (Central Processing Unit)

Question #300 Report Error

Which feature allows dynamic core frequency adjustment?

A. Static voltage

B. No adjustment

C. Fixed frequency

D. SpeedStep or Cool'n'Quiet

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Correct Answer: Option D

Explanation:
Intel and AMD power management.

This question belongs to: Computer CPU (Central Processing Unit)

CPU (Central Processing Unit) MCQs

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